Hierarchical execution to speed up pipeline interlock in mainframe computers

DOI10.1109/12.509910MaRDI QIDQ4420965zbMATH OpenOpenAlexFDO

Authors Yooichi Shintani, Toru Shonai, Hiroshi Kurokawa, Kazunori Kuriyama, Akira Yamaoka

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.509910

zbMATH Keywords

code optimizationcompiler

Mathematics Subject Classification ID

Computer system organization (68M99) Theory of compilers and interpreters (68N20)

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Cited in

(1)

• A performance and cost analysis of applying superscalar method to mainframe computers

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