On routability for FPGAs under faulty conditions

DOI10.1109/12.475125MaRDI QIDQ4421147zbMATH OpenOpenAlexFDO

Authors Kaushik Roy, Sudip Nag

Publication date 1995

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.475125

zbMATH Keywords

fault-tolerancearchitecture-synthesis

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited in

(6)

• scientific article; zbMATH DE number 1941064 (Why is no real title available?)
• scientific article; zbMATH DE number 1941076 (Why is no real title available?)
• scientific article; zbMATH DE number 1962862 (Why is no real title available?)
• scientific article; zbMATH DE number 1849100 (Why is no real title available?)
• In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults
• scientific article; zbMATH DE number 2172787 (Why is no real title available?)

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