On routability for FPGAs under faulty conditions

DOI10.1109/12.475125zbMATH Open1054.68525OpenAlexW2104136310MaRDI QIDQ4421147FDOQ4421147

Authors: Kaushik Roy, Sudip Nag 

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.475125

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zbMATH Keywords

fault-tolerancearchitecture-synthesis

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited In (6)

• Title not available (Why is that?)
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• In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults
• Title not available (Why is that?)

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