A fault-tolerant CEQRNS processing element for linear systolic array DSP applications

DOI10.1109/12.464390zbMATH Open1053.68518OpenAlexW2115736369MaRDI QIDQ4421186FDOQ4421186

Authors: Jeremy Smith, Fred Taylor 

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.464390

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zbMATH Keywords

redundancyVLSI designyield enhancement

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Mathematical problems of computer architecture (68M07)

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