Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics
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Publication:453526
DOI10.1007/s10703-011-0134-0zbMath1247.68162MaRDI QIDQ453526
Satrajit Chatterjee, Michael Kishinevsky
Publication date: 27 September 2012
Published in: Formal Methods in System Design (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10703-011-0134-0
formal verification; model checking; induction; proof; safety verification; network-on-chip; communication fabrics; high-level models; invariant synthesis; microarchitecture; synchronous model
68M10: Network design and communication in computer systems
68Q60: Specification and verification (program logics, model checking, etc.)