How to test a tree

DOI10.1002/(SICI)1097-0037(199810)32:3%3C189::AID-NET3%3E3.0.CO;2-GzbMATH Open1015.68019OpenAlexW2083564160MaRDI QIDQ4540076FDOQ4540076

Authors: Andrew B. Kahng, Gabriel Robins, Elizabeth A. Walkup 

Publication date: 21 July 2002

Full work available at URL: https://doi.org/10.1002/(sici)1097-0037(199810)32:3%3C189::aid-net3%3E3.0.co;2-g

Recommendations

• Diagnosis of Faults in Linear Tree Networks
• Testability of convergent tree circuits
• Connectivity testing
• Diagnosis of a regular-structure processor network
• scientific article; zbMATH DE number 522870

zbMATH Keywords

VLSI multichip module packaging

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (2)

• How to fit a tree in a box
• Searching for faulty leaves in binary trees

This page was built for publication: How to test a tree

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4540076)