Dynamic pipeline design of an adaptive binary arithmetic coder

DOI10.1109/82.964994MaRDI QIDQ4553221zbMATH OpenOpenAlexFDO

Authors Shiann Rong Kuang, Jer Min Jou, Ren der Chen, Yeu Horng Shiau

Publication date 25 November 2002

Published in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL https://semanticscholar.org/paper/86b4cb140a7559f6946dcb8a109846206eabb8a0

zbMATH Keywords

data compressionarithmetic codingVLSI architecturedynamic pipeline

Mathematics Subject Classification ID

Computer science aspects of computer-aided design (68U07) Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30)

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Cited in

(2)

• High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression
• scientific article; zbMATH DE number 1844687 (Why is no real title available?)

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