scientific article; zbMATH DE number 1798182

zbMATH Open0996.68588MaRDI QIDQ4553255FDOQ4553255

Authors: Miroslav N. Velev, Randal E. Bryant 

Publication date: 4 November 2002

Title of this publication is not available (Why is that?)

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Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

Cited In (8)

• Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic
• Producing and verifying extremely large propositional refutations
• Title not available (Why is that?)
• Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors.
• Building small equality graphs for deciding equality logic with uninterpreted functions
• EVC
• Automated Technology for Verification and Analysis
• Tools and Algorithms for the Construction and Analysis of Systems

Uses Software

• PVS
• CUDD
• Chaff
• Velev SAT Benchmarks

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