A formal verification method of error correction code processors over Galois-field arithmetic

zbMATH Open1395.94355MaRDI QIDQ4583845FDOQ4583845

Authors: Rei Ueno, Naofumi Homma, Takafumi Aoki 

Publication date: 3 September 2018

Full work available at URL: http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-26-number-1-2-2016/mvlsc-26-1-2-p-55-73/

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zbMATH Keywords

computer algebrapredicate logicReed-Solomon codeformal verificationGalois fielddesign methodology for arithmetic circuits

Mathematics Subject Classification ID

Cryptography (94A60) Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30) Combinatorial codes (94B25)

Cited In (4)

• Verifying the implementation of an error control code
• Title not available (Why is that?)
• Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry
• Verified Erasure Correction in Coq with MathComp and VST

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