scientific article; zbMATH DE number 1903354

zbMATH Open1010.68711MaRDI QIDQ4804897FDOQ4804897

Authors: Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers 

Publication date: 1 May 2003

Full work available at URL: http://link.springer.de/link/service/series/0558/bibs/2404/24040195.htm

Title of this publication is not available (Why is that?)

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zbMATH Keywords

Failure analysisTiming constraintsTimed circuitsTrace theoretic verification

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Reliability, testing and fault tolerance of networks and computer systems (68M15) Specification and verification (program logics, model checking, etc.) (68Q60) Fault detection; testing in circuits and networks (94C12)

Cited In (6)

• Reconciling fault-tolerant distributed computing and systems-on-chip
• Reasoning about synchronization in GALS systems
• Parameter synthesis for hierarchical concurrent real-time systems
• Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
• An inverse method for parametric timed automata
• Automated repair for timed systems

Uses Software

• VINAS-P

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