A systolic processor array for the quadrant interlocking elimination method
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Publication:4951741
DOI10.1080/00207160008804920zbMath0957.65017MaRDI QIDQ4951741
Publication date: 11 March 2001
Published in: International Journal of Computer Mathematics (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1080/00207160008804920
65Y05: Parallel numerical computation
65F05: Direct numerical methods for linear systems and matrix inversion
Cites Work