Performance planning

DOI10.1016/S0167-9260(99)00022-XzbMATH Open0938.68981OpenAlexW2914959071MaRDI QIDQ4955652FDOQ4955652

Authors: Ralph H. J. M. Otten, Robert K. Brayton 

Publication date: 4 June 2000

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0167-9260(99)00022-x

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zbMATH Keywords

VLSI circuits

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (8)

• Resource sharing combined with layout effects in high-level synthesis
• Title not available (Why is that?)
• On driving many long wires in a VLSI layout
• Optimal VLSI delay tuning by wire shielding
• Computer-aided planning and performance evaluation in organizations
• Group nearest-neighbor queries in the \(L_1\) plane
• Correct Hardware Design and Verification Methods
• Top-\(k\) Manhattan spatial skyline queries

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