Optimal VLSI delay tuning by wire shielding

DOI10.1007/S10957-016-0960-8MaRDI QIDQ328471zbMATH OpenOpenAlexFDO

Authors Binyamin Frankel, Shmuel Wimer

Publication date 20 October 2016

Published in Journal of Optimization Theory and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10957-016-0960-8

zbMATH Keywords

calculus of variationsdelay tuningwire shielding

Mathematics Subject Classification ID

Optimization of shapes other than minimal surfaces (49Q10) Optimality conditions for free problems in one independent variable (49K05)

Recommendations

• Performance optimization of VLSI interconnect layout
• scientific article; zbMATH DE number 3970689
• The complexity of VLSI power-delay optimization by interconnect resizing
• scientific article; zbMATH DE number 2127785
• Performance planning

This page was built for publication: Optimal VLSI delay tuning by wire shielding

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q328471)