Performance optimization of VLSI interconnect layout
From MaRDI portal
Recommendations
- scientific article; zbMATH DE number 750011
- scientific article; zbMATH DE number 2010437
- On VLSI interconnect optimization and linear ordering problem
- VLSI circuit performance optimization by geometric programming
- Interconnects in VLSI design
- Interconnect synthesis in high speed digital VLSI routing
- scientific article; zbMATH DE number 741127
Cited in
(7)- Computing a (1+)-approximate geometric minimum-diameter spanning tree
- Algorithms for synthesizing mechanical systems with maximal natural frequencies
- Interconnect synthesis in high speed digital VLSI routing
- Optimal VLSI delay tuning by wire shielding
- A survey on multi-net global routing for integrated circuits
- scientific article; zbMATH DE number 750011 (Why is no real title available?)
- VLSI circuit performance optimization by geometric programming
This page was built for publication: Performance optimization of VLSI interconnect layout
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3122470)