A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

DOI10.1109/TCSI.2017.2769721zbMATH Open1469.94225OpenAlexW2772357010MaRDI QIDQ4956715FDOQ4956715

Authors: Che-Wei Tien, S.-I. Liu 

Publication date: 2 September 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2017.2769721

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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