An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS
From MaRDI portal
Publication:4956740
DOI10.1109/TCSI.2016.2587621zbMATH Open1469.94211OpenAlexW2490203154MaRDI QIDQ4956740FDOQ4956740
Authors: Jae-Won Nam, Mike Shuo-Wei Chen
Publication date: 2 September 2021
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tcsi.2016.2587621
Recommendations
- A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 <formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS
- A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique
- A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching
This page was built for publication: An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4956740)