Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support

DOI10.1109/TC.2008.203zbMATH Open1367.65246OpenAlexW2153225046MaRDI QIDQ4975010FDOQ4975010

Authors: Dimitri Tan, Carl E. Lemonds, Michael J. Schulte 

Publication date: 8 August 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2008.203

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04) Numerical algorithms for specific classes of architectures (65Y10)

Cited In (2)

• Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
• Low-energy instruction precision assignment for multi-mode multiplier under accuracy and performance constraints

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