A High-Throughput LDPC Decoder Architecture With Rate Compatibility

DOI10.1109/TCSI.2010.2089551MaRDI QIDQ5010600zbMATH OpenOpenAlexFDO

Authors Kai Zhang, Xinming Huang, Zhongfeng Wang

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tcsi.2010.2089551

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Decoding (94B35)

Cited in

(6)

• A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet
• A Flexible NISC-Based LDPC Decoder
• A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
• A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes
• SCALABLE AND EFFICIENT IMPLEMENTATIONS OF THE LDPC DECODER USING RECONFIGURABLE MODELS
• High-throughput architectures for circular block-type low-density parity-check codes

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