MODELING METHODOLOGY FOR PERFORMANCE EVALUATION OF PARALLEL ARCHITECTURES A CASE STUDY, LCAP

DOI10.1142/S0129053389000305MaRDI QIDQ5203669zbMATH OpenOpenAlexFDO

Authors

Publication date 1989

Published in International Journal of High Speed Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1142/s0129053389000305

zbMATH Keywords

simulationparallel architecturesqueueing networkloosely coupled array of processors

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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Cited in

(2)

• scientific article; zbMATH DE number 1941109 (Why is no real title available?)
• Transient and steady-state performance modeling of parallel processors

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