Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

DOI10.1109/TC.2009.76zbMATH Open1368.68083MaRDI QIDQ5280768FDOQ5280768

Authors: Omer Khan, Sandip Kundu 

Publication date: 27 July 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Mathematical problems of computer architecture (68M07)

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