On high-speed computing with a programmable linear array

DOI10.1007/BF00127833zbMath1215.68283OpenAlexW2017276697MaRDI QIDQ547479

Zvi M. Kedem, Pei-Zong Lee

Publication date: 2 July 2011

Published in: The Journal of Supercomputing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf00127833

zbMATH Keywords

sortingparallel processingVLSItransitive closurepattern matchingsignal and image processingalgebraic computationsalgorithm transformationsdatabase operationsmatrix arithmeticnested loop algorithmsprogrammable systolic array

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites Work

• Modular Matrix Multiplication on a Linear Array
• The Design of Optimal Systolic Arrays
• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
• Mapping Homogeneous Graphs on Linear Arrays
• Time and Parallel Processor Bounds for Fortran-Like Loops
• Partitioned Matrix Algorithms for VLSI Arithmetic Systems
• The parallel execution of DO loops

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