Correct Hardware Design and Verification Methods

DOI10.1007/B93958zbMATH Open1179.68013OpenAlexW219731125MaRDI QIDQ5897071FDOQ5897071

Vineet Kahlon, E. Allen Emerson

Publication date: 5 February 2010

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/b93958

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Network protocols (68M12)

Cited In (15)

• Title not available (Why is that?)
• Title not available (Why is that?)
• Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols
• A case study on parametric verification of failure detectors
• Specification and verification of concurrent programs through refinements
• Title not available (Why is that?)
• Parameterized model checking of rendezvous systems
• Verifying Parameterized taDOM+ Lock Managers
• Parameterized model checking of networks of timed automata with Boolean guards
• An invariant-based approach to the verification of asynchronous parameterized networks
• Title not available (Why is that?)
• Deriving efficient cache coherence protocols through refinement
• Parameterized verification under TSO with data types
• Multi-parameterised compositional verification of safety properties
• Model Checking Parameterized Systems

Uses Software

• SNOOPY

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