Formal Methods for Hardware Verification

DOI10.1007/11757283zbMATH Open1182.68112OpenAlexW2475557998MaRDI QIDQ5899151FDOQ5899151

Authors: Nicola Bombieri, Franco Fummi, Graziano Pravadelli 

Publication date: 2 May 2007

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11757283

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Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

Cited In (9)

• An Embedded System's Design Verification Using Object-Oriented Simulation
• A VHDL-based HW/SW cosimulation of communication systems
• Dynamic and formal verification of embedded systems: A comparative survey
• Verification of embedded systems based on interval analysis
• Compositional Reasoning for Hardware/Software Co-verification
• A mixed level simulation environment for stepwise RTOS software refinement
• Performance estimation for an EDA tool-based HW/SW co-verification environment
• Hardware/Software Co-Verification: Models and Methods
• Title not available (Why is that?)

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