Formal Methods for Hardware Verification

DOI10.1007/11757283zbMATH Open1182.68115OpenAlexW2475557998MaRDI QIDQ5899153FDOQ5899153

Authors: Koen Claessen, Jan-Willem Roorda 

Publication date: 2 May 2007

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11757283

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Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

Cited In (8)

• Symbolic trajectory evaluation
• Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation
• On Bridging Simulation and Formal Verification
• A probabilistic and approximated approach to circuit-based formal verification
• Correct Hardware Design and Verification Methods
• Title not available (Why is that?)
• SAT-based methods for sequential hardware equivalence verification without synchronization
• Static Analysis

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