Computer Aided Verification

DOI10.1007/b11831zbMath1278.68160OpenAlexW1571340194MaRDI QIDQ5900678

Antoine Petit, Deepak D'Souza, P. Madhusudan, Patricia Bouyer

Publication date: 20 April 2010

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/b11831

Mathematics Subject Classification ID

Synthesis problems (93B50) Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (12)

Folk theorems on the determinization and minimization of timed automata ⋮ Synthesis of memory-efficient, clock-memory free, and non-Zeno safety controllers for timed systems ⋮ Verification and Control of Partially Observable Probabilistic Real-Time Systems ⋮ MR4UM: a framework for adding fault tolerance to UML state diagrams ⋮ Symbolic synthesis of masking fault-tolerant distributed programs ⋮ Timed Control with Observation Based and Stuttering Invariant Strategies ⋮ Synthesizing bounded-time 2-phase fault recovery ⋮ Verification and control of partially observable probabilistic systems ⋮ Supervisory Control with Partial Observations ⋮ Control and synthesis of non-interferent timed systems ⋮ The complexity of automated addition of fault-tolerance without explicit legitimate states ⋮ A supervisory control method for ensuring the conformance of real-time discrete event systems

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