Maximum realizability for linear temporal logic specifications
DOI10.1007/978-3-030-01090-4_27zbMATH Open1517.68229arXiv1804.00415OpenAlexW2964122198MaRDI QIDQ6109602FDOQ6109602
Authors: Rayna Dimitrova, Mahsa Ghasemi, Ufuk Topcu
Publication date: 28 July 2023
Published in: Automated Technology for Verification and Analysis (Search for Journal in Brave)
Full work available at URL: https://arxiv.org/abs/1804.00415
Recommendations
- Reactive synthesis with maximum realizability of linear temporal logic specifications
- Safraless LTL synthesis considering maximal realizability
- Reactive synthesis from signal temporal logic specifications
- Specification-guided controller synthesis for linear systems and safe linear-time temporal logic
- Synthesis from LTL specifications with mean-payoff objectives
Specification and verification (program logics, model checking, etc.) (68Q60) Automated systems (robots, etc.) in control theory (93C85) Temporal logic (03B44)
Cited In (2)
This page was built for publication: Maximum realizability for linear temporal logic specifications
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q6109602)