Reactive synthesis from signal temporal logic specifications
DOI10.1145/2728606.2728628zbMATH Open1366.68180DBLPconf/hybrid/RamanDSMS15OpenAlexW2095274657WikidataQ59813843 ScholiaQ59813843MaRDI QIDQ2988945FDOQ2988945
Authors: Vasumathi Raman, Alexandre Donzé, Dorsa Sadigh, Richard M. Murray, Sanjit A. Seshia
Publication date: 19 May 2017
Published in: Proceedings of the 18th International Conference on Hybrid Systems: Computation and Control (Search for Journal in Brave)
Full work available at URL: https://authors.library.caltech.edu/57535/
Recommendations
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- Reactive synthesis with maximum realizability of linear temporal logic specifications
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- Specification-guided controller synthesis for linear systems and safe linear-time temporal logic
Specification and verification (program logics, model checking, etc.) (68Q60) Synthesis problems (93B50) Automated systems (robots, etc.) in control theory (93C85)
Cites Work
Cited In (40)
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