A low-memory-access length-adaptive architecture for 2ⁿ-point FFT

DOI10.1007/S00034-014-9862-XzbMATH Open1401.94028OpenAlexW2012256636MaRDI QIDQ736386FDOQ736386

Authors Kuan-Hung Chen 

Publication date 4 August 2016

Published in Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s00034-014-9862-x

zbMATH Keywords

FFTenergy-efficientlength-adaptivelong-lengthVLSI architecture

Mathematics Subject Classification ID

Signal theory (characterization, reconstruction, filtering, etc.) (94A12) Numerical methods for discrete and fast Fourier transforms (65T50)

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Cites Work

• A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems
• High-speed and low-power split-radix FFT
• The efficient memory-based VLSI array designs for DFT and DCT

Cited In (2)

• An FFT performance model for optimizing general-purpose processor architecture
• Novel design of multiplier-less FFT processors

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