Correct hardware synthesis
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Publication:766178
DOI10.1007/S00236-011-0142-YzbMATH Open1234.68067OpenAlexW2023293472MaRDI QIDQ766178FDOQ766178
Authors: Augusto Sampaio, Juliano Iyoda, Juan Perna, Jim Woodcock 
Publication date: 23 March 2012
Published in: Acta Informatica (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s00236-011-0142-y
Recommendations
Theory of programming languages (68N15) Theory of compilers and interpreters (68N20) Specification and verification (program logics, model checking, etc.) (68Q60)
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Cited In (8)
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- Title not available (Why is that?)
- Mechanised wire-wise verification of Handel-C synthesis
- Mechanised wire-wise verification of Handel-C synthesis
- Title not available (Why is that?)
- Geometry of synthesis. IV: Compiling affine recursion into static hardware
- Geometry of synthesis. II: From games to delay-insensitive circuits
- An approach to the specification and verification of a hardware compilation scheme
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