Dense Gaussian networks: Suitable topologies for on-chip multiprocessors
From MaRDI portal
Publication:853772
DOI10.1007/S10766-006-0014-1zbMATH Open1103.68423OpenAlexW2156955579MaRDI QIDQ853772FDOQ853772
Authors: Carmen Martínez, Enrique Vallejo, R. Beivide, C. Izu, Miquel Moretó 
Publication date: 17 November 2006
Published in: International Journal of Parallel Programming (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10766-006-0014-1
Recommendations
- A high performance interconnection network for multiprocessor systems
- Comparing four classes of torus-based parallel architectures: network parameters and communication performance
- A bus-based semi-completely-connected network for high-performance on-chip systems
- A star-based I/O-bounded network for massively parallel systems
- Connections between two cycles --- a new design of dense processor interconnection networks
Cites Work
Cited In (10)
- Networks on chips -- using DQQB (Distributed queue quad-bus) on multi-CPU chips
- DESIGN OF A PARALLEL INTERCONNECT BASED ON COMMUNICATION PATTERN CONSIDERATIONS
- Efficient eight-regular circulants based on the Kronecker product
- Effective algorithm for finding shortest paths in dense Gaussian networks
- A bus-based semi-completely-connected network for high-performance on-chip systems
- A star-based I/O-bounded network for massively parallel systems
- Title not available (Why is that?)
- Dense bipartite circulants and their routing via rectangular twisted torus
- The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip
- Low Diameter Interconnections for Routing in High-Performance Parallel Systems
This page was built for publication: Dense Gaussian networks: Suitable topologies for on-chip multiprocessors
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q853772)
