Fault-aware communication mapping for noCs with guaranteed latency

DOI10.1007/S10766-006-0029-7zbMATH Open1115.68362OpenAlexW2081112779MaRDI QIDQ885017FDOQ885017

Authors: Sorin Manolache, Petru Eles, Zebo Peng 

Publication date: 7 June 2007

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-006-0029-7

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zbMATH Keywords

communication synthesisNetworks-on-chiptransient link failures

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites Work

• Tabu Search—Part I
• Virtual cut-through: A new computer communication switching technique

Cited In (3)

• A probabilistic spatial distribution model for wire faults in parallel network-on-chip links
• QoS-supported on-chip communication for multi-processors
• nDimNoC: Real-Time D-dimensional NoC

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