Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses
DOI10.1007/S10623-015-0084-4zbMATH Open1356.94098OpenAlexW636165048MaRDI QIDQ887428FDOQ887428
Authors: Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling, Hui Zhang, Xian De Zhang 
Publication date: 26 October 2015
Published in: Designs, Codes and Cryptography (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10623-015-0084-4
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constant weight codesbalanced sampling plancrosstalk avoidancelow power codepacking by triplespacking sampling plan avoiding adjacent units
Statistical block designs (62K10) Combinatorial codes (94B25) Combinatorial aspects of packing and covering (05B40) Triple systems (05B07)
Cites Work
- A Mathematical Theory of Communication
- Error detecting and error correcting codes
- Sampling plans excluding contiguous units
- A class of partial triple systems with applications in survey sampling
- Quadratic leaves of maximal partial triple systems
- The spectrum ofBSA(v, 3, λ; α) with α = 2,3
- Existence of balanced sampling plans avoiding cyclic distances
- New balanced sampling plans excluding adjacent units
- Title not available (Why is that?)
- Title not available (Why is that?)
Cited In (8)
- A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus
- Cyclic balanced sampling plans excluding contiguous units with block size four
- Improved asymptotically optimal error correcting codes for avoidance crosstalk type-IV on-chip data buses
- New optimal error-correcting codes for crosstalk avoidance in on-chip data buses
- Lightweight Error Correction Coding for System-Level Interconnects
- Loss reduction by transition-reducing coding of system buses
- Switching codes for delta-I noise reduction
- Scalable Optimal Test Patterns for Crosstalk-induced Faults on Deep Submicron Global Interconnects
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