Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

DOI10.1007/s10623-015-0084-4zbMath1356.94098OpenAlexW636165048MaRDI QIDQ887428

Alan C. H. Ling, Yeow Meng Chee, Charles J. Colbourn, Hui Zhang, Xian De Zhang

Publication date: 26 October 2015

Published in: Designs, Codes and Cryptography (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10623-015-0084-4

zbMATH Keywords

constant weight codesbalanced sampling plancrosstalk avoidancelow power codepacking by triplespacking sampling plan avoiding adjacent units

Mathematics Subject Classification ID

Statistical block designs (62K10) Triple systems (05B07) Combinatorial codes (94B25) Combinatorial aspects of packing and covering (05B40)

Related Items

Cyclic balanced sampling plans excluding contiguous units with block size four ⋮ Improved asymptotically optimal error correcting codes for avoidance crosstalk type-IV on-chip data buses ⋮ New optimal error-correcting codes for crosstalk avoidance in on-chip data buses

Uses Software

• Cliquer

Cites Work

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