Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

DOI10.1007/S10623-015-0084-4MaRDI QIDQ887428zbMATH OpenOpenAlexFDO

Authors Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling, Hui Zhang, Xian De Zhang

Publication date 26 October 2015

Published in Designs, Codes and Cryptography (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10623-015-0084-4

zbMATH Keywords

constant weight codesbalanced sampling plancrosstalk avoidancelow power codepacking by triplespacking sampling plan avoiding adjacent units

Mathematics Subject Classification ID

Statistical block designs (62K10) Combinatorial codes (94B25) Combinatorial aspects of packing and covering (05B40) Triple systems (05B07)

Recommendations

• New optimal error-correcting codes for crosstalk avoidance in on-chip data buses
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• A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus
• Scalable Optimal Test Patterns for Crosstalk-induced Faults on Deep Submicron Global Interconnects
• Switching codes for delta-I noise reduction

Cites work

• scientific article; zbMATH DE number 3948279 (Why is no real title available?)
• scientific article; zbMATH DE number 933214 (Why is no real title available?)
• A Mathematical Theory of Communication
• A class of partial triple systems with applications in survey sampling
• Error detecting and error correcting codes
• Existence of balanced sampling plans avoiding cyclic distances
• New balanced sampling plans excluding adjacent units
• Quadratic leaves of maximal partial triple systems
• Sampling plans excluding contiguous units
• The spectrum ofBSA(v, 3, λ; α) with α = 2,3

Cited in

(9)

• Cyclic balanced sampling plans excluding contiguous units with block size four
• Switching codes for delta-I noise reduction
• Improved asymptotically optimal error correcting codes for avoidance crosstalk type-IV on-chip data buses
• Scalable Optimal Test Patterns for Crosstalk-induced Faults on Deep Submicron Global Interconnects
• Loss reduction by transition-reducing coding of system buses
• New optimal error-correcting codes for crosstalk avoidance in on-chip data buses
• Lightweight Error Correction Coding for System-Level Interconnects
• A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus
• Combinatorial constructions of optimal low-power error-correcting cooling codes

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