Two dimensional processor array with a reconfigurable bus system is at least as powerful as CRCW model

DOI10.1016/0020-0190(90)90182-WzbMATH Open0703.68041OpenAlexW2084386794MaRDI QIDQ916359FDOQ916359

Authors: Biing-Feng Wang, Gen-Huey Chen 

Publication date: 1990

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(90)90182-w

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zbMATH Keywords

computational complexityprocessor arraySIMDreconfigurable busCRCW shared-memory computerMIMD

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Complexity of computation (including implicit computational complexity) (03D15)

Cites Work

• Parallel computation and conflicts in memory access
• Efficient parallel convex hull algorithms
• Ultracomputers
• Constant time sorting on a processor array with a reconfigurable bus system
• Bus automata and immediate languages

Cited In (10)

• Optimal simulation of multidimensional reconfigurable meshes by two- dimensional reconfigurable meshes
• Title not available (Why is that?)
• Fast algorithms for lowest common ancestors on a processor array with reconfigurable buses
• Simulating the CRCW PRAM on reconfigurable networks
• Collapsing the hierarchy of parallel computational models
• Sorting and computing convex hulls on processor arrays with reconfigurable bus systems
• Multiple search problem on reconfigurable meshes
• Simulating shared memory in real time: On the computation power of reconfigurable architectures
• Relating the power of the multiple associative computing (MASC) model to that of reconfigurable bus-based models
• Simulations between two reconfigurable mesh models

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