Collapsing the hierarchy of parallel computational models

DOI10.1142/S0129054110007350zbMATH Open1192.68273MaRDI QIDQ3569286FDOQ3569286

Authors: Stefan D. Bruda, Yuanqiao Zhang 

Publication date: 18 June 2010

Published in: International Journal of Foundations of Computer Science (Search for Journal in Brave)

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zbMATH Keywords

parallel computationreal-time computationreconfigurable multiple bus machineparallel random access machinegraph accessibility problemreconfigurable networkbroadcast with selective reductionconcurrent-read concurrent-write conflict resolution rules

Mathematics Subject Classification ID

Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Network design and communication in computer systems (68M10)

Cites Work

• Title not available (Why is that?)
• Parity, circuits, and the polynomial-time hierarchy
• Title not available (Why is that?)
• Simulation of Parallel Random Access Machines by Circuits
• Two dimensional processor array with a reconfigurable bus system is at least as powerful as CRCW model
• The complexity of reconfiguring network models
• Optimal BSR solutions to several convex polygon problems

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