A generic algorithm for one-dimensional homotopic compaction

DOI10.1007/BF01759037MaRDI QIDQ916367zbMATH OpenFDO

Authors F. Miller Maley

Publication date 1991

Published in Algorithmica (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BF01759037

zbMATH Keywords

VLSI layoutconstraint solvingriver routingcut conditionshomotopic compactionhomotopic routingjog insertionknock-knee routingroutabilitywire length minimizationwire routing

Mathematics Subject Classification ID

Circuits, networks (94C99) Parallel algorithms in computer science (68W10)

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Cites work

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• A Linear-Time Algorithm for the Homotopic Routing Problem in Grid Graphs
• A mixed-integer linear programming problem which is efficiently solvable
• On the solution of inequality systems relevant to IC-layout
• Parity conditions in homotopic knock-knee routing

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• New algorithms based on a multiple storage quadtree for hierarchical compaction of VLSI mask layout
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• scientific article; zbMATH DE number 3894985 (Why is no real title available?)
• A framework for 1-D compaction with forbidden region avoidance
• On counting pairs of intersecting segments and off-line triangle range searching
• Fast algorithms for one-dimensionsal compaction with jog insertion
• scientific article; zbMATH DE number 3852448 (Why is no real title available?)
• Minimizing total wire length during 1-dimensional compaction
• Parity conditions in homotopic knock-knee routing
• Single-layer cylindrical compaction
• A faster one-dimensional topological compaction algorithm with jog insertion

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