Satisfiability checking using Boolean expression diagrams

DOI10.1007/3-540-45319-9_4MaRDI QIDQ2769575zbMATH OpenFDO

Authors Henrik Reif Andersen, Henrik Hulgaard, Poul Frederick Williams

Publication date 5 February 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2031/20310039

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Recommendations

• Boolean expression diagrams
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Cited in

(9)

• Satisfiability testing for Boolean formulas using -trees
• Formal verification based on Boolean expression diagrams
• Boolean expression diagrams
• Boolean satisfiability with transitivity constraints
• Combining decision diagrams and SAT procedures for efficient symbolic model checking
• Verification diagrams revisited: Disjunctive invariants for easy verification
• Towards an efficient tableau method for Boolean circuit satisfiability checking
• Boolean satisfiability with transitivity constraints
• A moderately exponential time algorithm for k-IBDD satisfiability

Describes a project that uses

Uses Software

• SATLIB
• SATO

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