Scheduling instructions with uncertain latencies in asynchronous architectures
From MaRDI portal
Recommendations
- Fast optimal instruction scheduling for single-issue processors with arbitrary latencies
- Scheduling of computational processes in real-time distributed systems with uncertain task execution times
- Instruction scheduling with timing constraints on a single RISC processor with 0/1 latencies
- scientific article; zbMATH DE number 2112980
- Scheduling with uncertain processing times in mixed-criticality systems
- Scheduling imprecise computation tasks on uniform processors
Cited in
(2)
This page was built for publication: Scheduling instructions with uncertain latencies in asynchronous architectures
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4537027)