Some Complexity Results for SystemVerilog Assertions

DOI10.1007/11817963_21MaRDI QIDQ5756748zbMATH OpenOpenAlexFDO

Authors Doron Bustan, John W. Havlicek

Publication date 5 September 2007

Published in Computer Aided Verification (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/11817963_21

Mathematics Subject Classification ID

Computational difficulty of problems (lower bounds, completeness, difficulty of approximation, etc.) (68Q17) Analysis of algorithms and problem complexity (68Q25) Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60)

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Cited in

(7)

• Groebner bases based verification solution for SystemVerilog concurrent assertions
• Functional specification of hardware via temporal logic
• Wu's characteristic set method for SystemVerilog assertions verification
• Specification languages for stutter-invariant regular properties
• Safety and Liveness, Weakness and Strength, and the Underlying Topological Relations
• Automated Technology for Verification and Analysis
• On regular temporal logics with past

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