The following pages link to Shuvra S. Bhattacharyya (Q1773577):
Displayed 16 items.
- High-level synthesis of DSP applications using adaptive negative cycle detection (Q1773578) (← links)
- Intermediate representations for design automation of multiprocessor DSP systems (Q1857127) (← links)
- Logic foundry: Rapid prototyping for FPGA-based DSP systems (Q1886911) (← links)
- Multidimensional exploration of software implementations for DSP algorithms (Q1974492) (← links)
- Analysis of dataflow programs with interval-limited data-rates (Q2432195) (← links)
- Resynchronization for multiprocessor DSP systems (Q2724315) (← links)
- (Q4471675) (← links)
- Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation (Q4564681) (← links)
- Contention-conscious transaction ordering in multiprocessor DSP systems (Q4587672) (← links)
- A Wideband Front-End Receiver Implementation on GPUs (Q4619555) (← links)
- PRUNE: Dynamic and Decidable Dataflow for Signal Processing on Heterogeneous Platforms (Q4621575) (← links)
- (Q4790576) (← links)
- Generating compact code from dataflow specifications of multirate signal processing algorithms (Q4836858) (← links)
- (Q4888827) (← links)
- Parameterized dataflow modeling for DSP systems (Q5353559) (← links)
- The hierarchical timing pair model for multirate DSP applications (Q5356860) (← links)