The following pages link to Stefano Tonetta (Q479825):
Displaying 32 items.
- Quantifier-free encoding of invariants for hybrid systems (Q479826) (← links)
- Implicit semi-algebraic abstraction for polynomial dynamical systems (Q832202) (← links)
- HRELTL: a temporal logic for hybrid systems (Q897648) (← links)
- Tightening the contract refinements of a system architecture (Q1654565) (← links)
- Formal specification and verification of dynamic parametrized architectures (Q2024379) (← links)
- Certifying proofs for SAT-based model checking (Q2058379) (← links)
- \(\mathsf{GR}(1)\) is equivalent to \(\mathsf{R}(1)\) (Q2094389) (← links)
- Diagnosability of fair transition systems (Q2152493) (← links)
- SMT-based satisfiability of first-order LTL with event freezing functions and metric operators (Q2182731) (← links)
- Loop summarization using state and transition invariants (Q2248058) (← links)
- Infinite-state invariant checking with IC3 and predicate abstraction (Q2363814) (← links)
- GSTE is partitioned model checking (Q2385196) (← links)
- SMT-based scenario verification for hybrid systems (Q2441772) (← links)
- From Sequential Extended Regular Expressions to NFA with Symbolic Labels (Q3073625) (← links)
- (Q3384172) (← links)
- Formal Design of Asynchronous Fault Detection and Identification Components using Temporal Epistemic Logic (Q3449766) (← links)
- Formal Safety Assessment via Contract-Based Design (Q3457781) (← links)
- Loop Summarization Using Abstract Transformers (Q3540068) (← links)
- Requirements Validation for Hybrid Systems (Q3636860) (← links)
- Infinite-State Liveness-to-Safety via Implicit Abstraction and Well-Founded Relations (Q4633542) (← links)
- Safe Decomposition of Startup Requirements: Verification and Synthesis (Q5039507) (← links)
- Computer Aided Verification (Q5312902) (← links)
- Boolean Abstraction for Temporal Logic Satisfiability (Q5429344) (← links)
- Computer Aided Verification (Q5716576) (← links)
- Property-Driven Partitioning for Abstraction Refinement (Q5758119) (← links)
- Correct Hardware Design and Verification Methods (Q5897061) (← links)
- Verification Modulo theories (Q6056642) (← links)
- Assumption-based runtime verification (Q6102167) (← links)
- A first-order logic characterization of safety and co-safety languages (Q6135783) (← links)
- Searching for ribbon-shaped paths in fair transition systems (Q6535577) (← links)
- Expressiveness of extended bounded response \textsf{LTL} (Q6649521) (← links)
- Extended bounded response LTL: a new safety fragment for efficient reactive synthesis (Q6661746) (← links)
