The following pages link to (Q4806206):
Displaying 12 items.
- IF-2.0 (Q15835) (← links)
- Translating FSP into LOTOS and networks of automata (Q613134) (← links)
- Translating Java for multiple model checkers: The Bandera back-end (Q816196) (← links)
- Detecting synchronisation of biological oscillators by model checking (Q969176) (← links)
- Bounded determinization of timed automata with silent transitions (Q1699228) (← links)
- Scaling up livelock verification for network-on-chip routing algorithms (Q2152663) (← links)
- Scheduling with timed automata (Q2368955) (← links)
- Dynamic and formal verification of embedded systems: A comparative survey (Q2506271) (← links)
- Language-Oriented Formal Analysis: a Case Study on Protocols and Distributed Systems (Q2870335) (← links)
- Performance Evaluation of Schedulers in a Probabilistic Setting (Q3172839) (← links)
- Approximating Continuous Systems by Timed Automata (Q3506869) (← links)
- The Unmet Challenge of Timed Systems (Q5170750) (← links)
