Square-Rooting Algorithms for High-Speed Digital Circuits

DOI10.1109/TC.1985.1676618MaRDI QIDQ3680276zbMATH OpenOpenAlexFDO

Authors Stanisław Majerski

Publication date 1985

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1985.1676618

zbMATH Keywords

binary square rootingparallel reduction of summandsredundant number notation

Mathematics Subject Classification ID

Symbolic computation and algebraic computation (68W30)

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