Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

DOI10.1109/TC.2007.70766MaRDI QIDQ4564251zbMATH OpenOpenAlexFDO

Authors Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward

Publication date 12 June 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2007.70766

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

Cited in

(2)

• Fault tolerant control of asynchronous sequential machines with transient faults in non-fundamental mode
• Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller

This page was built for publication: Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4564251)