TILOS

swMATH11680MaRDI QIDQ23620FDOQ23620

Author name not available (Why is that?)

Official website: http://rd.springer.com/chapter/10.1007/978-1-4615-0292-0_23

Cited In (8)

• A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing
• Title not available (Why is that?)
• A tutorial on geometric programming
• Transistor sizing of custom high-performance digital circuits with parametric yield considerations
• A convex programming solution for gate-sizing with pipelining constraints
• GGPLAB
• JiffyTune
• Approximation scheme for restricted discrete gate sizing targeting delay minimization

This page was built for software: TILOS