TILOS
From MaRDI portal
Cited in
(9)- Approximation scheme for restricted discrete gate sizing targeting delay minimization
- A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing
- A tutorial on geometric programming
- Transistor sizing of custom high-performance digital circuits with parametric yield considerations
- RITUAL
- GGPLAB
- JiffyTune
- scientific article; zbMATH DE number 5042863 (Why is no real title available?)
- A convex programming solution for gate-sizing with pipelining constraints
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