TLRW
From MaRDI portal
Cited in
(13)- A single-version STM that is multi-versioned permissive
- Brief Announcement: On Implementing Software Transactional Memory in the C++ Memory Model
- SMV: selective multi-versioning STM
- STMBench7
- STAMP
- DiSTM
- LORAIN
- NOrec
- JudoSTM
- RingSTM
- TMunit
- \(\mathrm {TM}^{2}\mathrm {C}\): a software transactional memory for many-cores
- Synchrobench
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