Temporal logic for scenario-based specifications

DOI10.1007/978-3-540-31980-1_29MaRDI QIDQ5703777zbMATH OpenOpenAlexFDO

Authors Hillel Kugler, David Harel, Amir Pnueli, Yves Bontemps, Yuan Lu

Publication date 10 November 2005

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/b107194

Mathematics Subject Classification ID

Temporal logic (03B44) Logic in computer science (03B70) Specification and verification (program logics, model checking, etc.) (68Q60)

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Cited in

(13)

• GR(1)*: GR(1) specifications extended with existential guarantees
• Event-driven temporal logic pattern for control software requirements specification
• Using temporal logics of knowledge for specification and verification -- a case study
• Improving translation of live sequence charts to temporal logic
• On the Expressive Power of Live Sequence Charts
• Speeding up model checking of timed-models by combining scenario specialization and live component analysis
• Multi-modal scenarios revisited: a net-based representation
• Verifying Communication Protocols Using Live Sequence Chart Specifications
• Some Results on the Expressive Power and Complexity of LSCs
• CTRL: extension of CTL with regular expressions and fairness operators to verify genetic regulatory networks
• Modal scenarios as automata
• Scenario-based verification of real-time systems using UPPAAL
• GR(1)*: GR(1) specifications extended with existential guarantees

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