The Weighted Syndrome Sums Approach to VLSI Testing

DOI10.1109/TC.1981.1675744MaRDI QIDQ3918055zbMATH OpenOpenAlexFDO

Authors Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith

Publication date 1981

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1981.1675744

zbMATH Keywords

partitioningself-testingsyndrome-testable design

Mathematics Subject Classification ID

Cited in

(3)

• The use of linear sums in exhaustive testing
• A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
• Graph partitioning applied to the logic testing of combinational circuits

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