The impact of cache coherence protocols on parallel logic programming systems

DOI10.1007/3-540-44957-4_86MaRDI QIDQ2767148zbMATH OpenFDO

Authors Inês de Castro Dutra, Vítor Costa, Ricardo Bianchini

Publication date 28 January 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-44957-4_86

zbMATH Keywords

cache coherence protocolsDSM architectureslogic programmingparallelismperformance evaluation

Mathematics Subject Classification ID

Logic programming (68N17) Computing methodologies and applications (68U99)

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