Value prediction as a cost-effective solution to improve embedded processors performance

DOI10.1007/3-540-44942-6_14MaRDI QIDQ4472355zbMATH OpenFDO

Authors Silvia del Pino, Luis Piñuel, Rafael A. Moreno, F. Tirado

Publication date 4 August 2004

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/1981/19810181.htm

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Recommendations

• An efficient value predictor dynamically using loop and locality properties
• Improving conditional branch prediction on speculative multithreading architectures
• Modeling And Performance Evaluation Of Branch And Value Prediction In Ilp Processors
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Cited in

(8)

• Evaluation and choice of various branch predictors for low-power embedded processor
• Influence of compiler optimizations on value prediction
• The effect of the speculation depth on the performance of superscalar architectures
• Studying new ways for improving adaptive history length branch predictors
• Improving conditional branch prediction on speculative multithreading architectures
• Modeling And Performance Evaluation Of Branch And Value Prediction In Ilp Processors
• Increasing instruction-level parallelism with instruction precomputation
• An efficient value predictor dynamically using loop and locality properties

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