Verisym: Verifying circuits by symbolic simulation

DOI10.1023/A:1022977607142MaRDI QIDQ1870230zbMATH OpenOpenAlexFDO

Authors Yanyan Li

Publication date 11 May 2003

Published in Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1022977607142

zbMATH Keywords

symbolic simulationcircuit extractionformal property checkingmemory verification

Mathematics Subject Classification ID

Abstract data types; algebraic specification (68Q65)

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