Reveal: A Formal Verification Tool for Verilog Designs

DOI10.1007/978-3-540-89439-1_25MaRDI QIDQ5505565zbMATHOpenAlexFDO

Authors Zaher Andraus, Mark H. Liffiton, Karem A. Sakallah

Publication date 27 January 2009

Published in Logic for Programming, Artificial Intelligence, and Reasoning (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-540-89439-1_25

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

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Describes a project that uses

Uses Software

• CEGAR

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