Reveal: A Formal Verification Tool for Verilog Designs

DOI10.1007/978-3-540-89439-1_25zbMATH Open1182.68111OpenAlexW1644782203MaRDI QIDQ5505565FDOQ5505565

Authors: Zaher Andraus, Mark H. Liffiton, Karem A. Sakallah 

Publication date: 27 January 2009

Published in: Logic for Programming, Artificial Intelligence, and Reasoning (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-89439-1_25

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Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (12)

• Title not available (Why is that?)
• Fast, flexible MUS enumeration
• Quantified maximum satisfiability
• Automated Technology for Verification and Analysis
• Supercharging plant configurations using Z3
• Title not available (Why is that?)
• Title not available (Why is that?)
• Reveal
• Title not available (Why is that?)
• A coverification framework
• DSValidator: an automated counterexample reproducibility tool for digital systems
• What's decidable about program verification modulo axioms?

Uses Software

• CEGAR

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