Reveal: A Formal Verification Tool for Verilog Designs

DOI10.1007/978-3-540-89439-1_25zbMATH Open1182.68111OpenAlexW1644782203MaRDI QIDQ5505565FDOQ5505565

Authors: Zaher Andraus, Mark H. Liffiton, Karem A. Sakallah 

Publication date: 27 January 2009

Published in: Logic for Programming, Artificial Intelligence, and Reasoning (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-89439-1_25

Recommendations

• scientific article; zbMATH DE number 139802
• Rewriting logic as a framework for generic verification tools
• scientific article; zbMATH DE number 1428923
• Publication:3030255
• scientific article; zbMATH DE number 139808
• Verisym: Verifying circuits by symbolic simulation
• Rewriting environment for arithmetic circuit verification

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (11)

• Title not available (Why is that?)
• Fast, flexible MUS enumeration
• Quantified maximum satisfiability
• Automated Technology for Verification and Analysis
• Supercharging plant configurations using Z3
• Title not available (Why is that?)
• Title not available (Why is that?)
• Reveal
• What’s Decidable About Program Verification Modulo Axioms?
• Title not available (Why is that?)
• A coverification framework

Uses Software

• CEGAR

This page was built for publication: Reveal: A Formal Verification Tool for Verilog Designs

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5505565)